cy23s08 3.3v zero delay buffer cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 38-07265 rev. *h revised november 3, 2008 features zero input output propagation de lay, adjustable by capacitive load on fbk input multiple configurations (see table 3 on page 3) multiple low-skew outputs ? 45 ps typical output-output skew (?1) ? two banks of four outputs, three-stateable by two select in- puts 10 mhz to 140 mhz operating range 65 ps typical cycle- cycle jitter (?1, ?1h) advanced 0.65 cmos technology space saving 16-pin, 150-mil soic/tssop packages 3.3v operation spread aware functional description the cy23s08 is a 3.3v zero delay buffer designed to distribute high speed clocks in pc, workstation, datacom, telecom, and other high performance applications. the part has an on-chip pll which locks to an input clock presented on the ref pin. the pll feedback must be driven into the fbk pin, and obtained from one of the outputs. the input-to-output propagation delay is less than 350 ps, and output-to-output skew is less than 250 ps. the cy23s08 has two banks of four outputs each, which can be controlled by the select inputs as shown in table 2 on page 3. if all output clocks are not requir ed, bank b can be three-stated. the select inputs also enable the input clock to be directly applied to the output for chip and system testing purposes. the cy23s08 pll enters a power down state when there are no rising edges on the ref input. in this mode, all outputs are three-stated and the pll is turned off, resulting in less than 50 a of current draw. the pll shuts down in two additional cases as shown in table 2 on page 3. multiple cy23s08 devices acc ept the same input clock and distribute it in a system. in this case, the skew between the outputs of two devices is less than 700 ps. the cy23s08 is available in five different configurations, as shown in table 3 on page 3. the cy23s08?1 is the base part, where the output frequencies equal the reference if there is no counter in the feedback path. the cy23s08?1h is the high drive version of the ?1, and rise and fall times on this device are much faster. the cy23s08?2 enables the user to obtain 2x and 1x frequencies on each output b ank. the exact configuration and output frequencies depends on wh ich output drives the feedback pin. the cy23s08?2h is the high drive version of the ?2, and rise and fall times on this device are much faster. the cy23s08?3 enables the user to obtain 4x and 2x frequencies on the outputs. the cy23s08?4 enables the user to obtain 2x clocks on all outputs. thus, the part is versat ile, and can be used in a variety of applications. logic block diagram ref clka1 clka2 clka3 clka4 fbk pll mux select input decoding s2 s1 clkb1 clkb2 clkb3 clkb4 /2 extra divider (?2, ?2h, ?3) /2 extra divider (?3, ?4) [+] feedback
cy23s08 document #: 38-07265 rev. *h page 2 of 10 pinouts figure 1. 16-pin soic package table 1. pin definition - 16-pin soic package pin signal description 1ref [2] input reference frequency, 5v tolerant input 2 clka1 [3] clock output, bank a 3 clka2 [3] clock output, bank a 4v dd 3.3v supply 5 gnd ground 6 clkb1 [3] clock output, bank b 7 clkb2 [3] clock output, bank b 8s2 [4] select input, bit 2 9s1 [4] select input, bit 1 10 clkb3 [3] clock output, bank b 11 clkb4 [3] clock output, bank b 12 gnd ground 13 v dd 3.3v supply 14 clka3 [3] clock output, bank a 15 clka4 [3] clock output, bank a 16 fbk pll feedback input 9 16 fbk clka4 clka3 v dd gnd clkb4 clkb3 s1 1 2 3 4 5 6 7 8 10 11 12 13 14 15 ref clka1 clka2 v dd gnd clkb1 clkb2 s2 top view soic notes 1. output phase is indeterminant (0 or 180 from input cl ock). if phase integrity is required, use the cy23s08?2. 2. weak pull down. 3. weak pull down on all outputs. 4. weak pull ups on these inputs. [+] feedback
cy23s08 document #: 38-07265 rev. *h page 3 of 10 spread aware many systems designed now use the spread spectrum frequency timing generation (ssftg) technology. cypress is one of the pioneers of ssftg development, and designed this product so as not to filter off the spread spectrum feature of the reference i nput, assuming it exists. when a zero delay buffer does not pass through the ss feature, the result is a significant amount of tracki ng skew which may cause problems in systems requiring synchronization. for more details on spread spectrum timing technology, please see cypress?s application note emi suppression techniques with spread spectrum frequency timing generator (ssftg) ics . table 2. select input decoding s2 s1 clock a1?a4 clock b1?b4 output source pll shutdown 0 0 three-state three-state pll y 0 1 driven three-state pll n 1 0 driven driven reference y 1 1 driven driven pll n table 3. available cy23s08 configurations device feedback from bank a frequency bank b frequency cy23s08?1 bank a or bank b reference reference cy23s08?1h bank a or bank b reference reference cy23s08?2 bank a reference reference/2 cy23s08?2h bank a reference reference/2 cy23s08?2 bank b 2 x reference reference cy23s08?2h bank b 2 x reference reference cy23s08?3 bank a 2 x reference reference or reference [1] cy23s08?3 bank b 4 x reference 2 x reference cy23s08?4 bank a or bank b 2 x reference 2 x reference [+] feedback
cy23s08 document #: 38-07265 rev. *h page 4 of 10 maximum ratings supply voltage to ground potentia l................?0.5v to +7.0v dc input voltage (except ref) .............. ?0.5v to v dd + 0.5v dc input voltage ref ........................................... ?0.5 to 7v storage temperature ................ .............. ... ?65c to +150c max soldering temperature (10 sec.) ........................ 260c junction temperature ................................................. 150c static discharge voltage (per mil-std-883, method 3015) ............ .............. ... >2000v operating conditions for cy23s08sc- xx commercial temperature devices parameter [5] description min max unit v dd supply voltage 3.0 3.6 v t a operating temperat ure (ambient temperature) 0 70 c c l load capacitance, below 100 mhz ? 30 pf load capacitance, from 100 mhz to 140 mhz ? 15 pf c in input capacitance [6] ?7 pf electrical characteristics for cy23s08s c-xx commercial temperature devices parameter description test conditions min max unit v il input low voltage ? 0.8 v v ih input high voltage 2.0 ? v i il input low current v in = 0v ? 50.0 a i ih input high current v in = v dd ? 100.0 a v ol output low voltage [7] i ol = 8 ma (?1, ?2, ?3, ?4) i ol = 12 ma (-1h, -2h) ?0.4 v v oh output high voltage [7] i oh = ?8 ma (?1, ?2, ?3, ?4) i oh = ?12 ma (?1h, ?2h) 2.4 ? v i dd (pd mode) power down supply current ref = 0 mhz ? 12.0 a i dd supply current unloaded outputs, 100-mhz ref, select inputs at v dd or gnd ? 45.0 ma ? 70.0 (?1h, ?2h) ma unloaded outputs, 66-mhz ref (?1,?2,?3,?4) ? 32.0 ma unloaded outputs, 33-mhz ref (?1,?2,?3,?4) ? 18.0 ma switching characteristics for cy23s08s c-xx commercial temperature devices parameter [8] name test conditions min typ. max unit t1 output frequency 30-pf load, ?1, ?1h, ?2, ?3 devices 10 ? 100 mhz t1 output frequency 30-pf load, ?4 devices 15 ? 100 mhz t1 output frequency 20-pf load, ?1h device 10 ? 133.3 mhz t1 output frequency 15-pf load, ?1, ?2, ?3, devices 10 ? 140.0 mhz t1 output frequency 15-pf load, ?4 devices 15 ? 140.0 mhz duty cycle [7] = t 2 t 1 (?1,?2,?3,?4,?1h, -2h) measured at v dd /2, f out = 66.66 mhz 30-pf load 40.0 50.0 60.0 % duty cycle [7] = t 2 t 1 (?1,?2,?3,?4,?1h, -2h) measured at v dd /2, f out <66.66 mhz 15-pf load 45.0 50.0 55.0 % notes 5. multiple supplies: the voltage on any input or io pin cannot exceed the power pin during power up. power supply sequencing is not required. 6. applies to both ref clock and fbk. 7. parameter is guaranteed by design and char acterization. not 100% tested in production. 8. all parameters are specified with loaded outputs. [+] feedback
cy23s08 document #: 38-07265 rev. *h page 5 of 10 t3 rise time [7] (?1, ?2, ?3, ?4) measured between 0.8v and 2.0v, 30-pf load ? ? 2.20 ns t3 rise time [7] (?1, ?2, ?3, ?4) measured between 0.8v and 2.0v, 15-pf load ? ? 1.50 ns t3 rise time [7] (?1h, -2h) measured between 0.8v and 2.0v, 30-pf load ? ? 1.50 ns t 4 fall time [7] (?1, ?2, ?3, ?4) measured between 0.8v and 2.0v, 30-pf load ? ? 2.20 ns t 4 fall time [7] (?1, ?2, ?3, ?4) measured between 0.8v and 2.0v, 15-pf load ? ? 1.50 ns t 4 fall time [7] (?1h, 2h) measured between 0.8v and 2.0v, 30-pf load ? ? 1.25 ns t 5 output to output skew on same bank (?1) [7] all outputs equally loaded 45 200 ps output to output skew on same bank (?1h,?2,?2h,?3) [7] all outputs equally loaded ? 105 150 ps output to output skew on same bank (?4) [7] all outputs equally loaded ? 70 100 ps output to output skew (?1h, -2h) all outputs equally loaded ? ? 200 ps output bank a to output bank b skew (?1,?2, ?3) all outputs equally loaded ? ? 300 ps output bank a to output bank b skew (?4) all outputs equally loaded ? ? 215 ps output bank a to output bank b skew (?1h) all outputs equally loaded ? ? 250 ps t 6 delay, ref rising edge to fbk rising edge [7] measured at v dd /2 ?250 ? + 275 ps t 7 device to device skew [7] measured at v dd /2 on the fbk pins of devices ??700ps t 8 output slew rate [7] measured between 0.8v and 2.0v on ?1h, ?2h device using test circuit #2 1? v/ns t j cycle to cycle jitter [7] (?1, ?1h) measured at 66.67 mhz, loaded outputs, 15, 30-pf loads: 133 mhz, 15-pf load ?65125ps cycle to cycle jitter [7] (?2) measured at 66.67 mhz, loaded outputs, 15-pf load ?85300ps cycle to cycle jitter [7] (?2) measured at 66.67 mhz, loaded outputs, 30-pf load ??400ps t j cycle to cycle jitter [7] (?3,?4) measured at 66.67 mhz, loaded outputs 15, 30-pf loads ??200ps t lock pll lock time [7] stable power supply, valid clocks presented on ref and fbk pins ??1.0ms switching characteristics for cy23s08s c-xx commercial temperature devices (continued) parameter [8] name test conditions min typ. max unit [+] feedback
cy23s08 document #: 38-07265 rev. *h page 6 of 10 switching waveforms figure 2. duty cycle timing figure 3. all outputs rise and fall time figure 4. ou tput-output skew figure 5. input-output propagation delay figure 6. device-device skew t 1 t 2 1.4v 1.4v 1.4v output t 3 3.3v 0v 0.8v 2.0v 2.0v 0.8v t 4 1.4v t 5 output output 1.4v v dd /2 t 6 input fbk v dd /2 v dd /2 v dd /2 t 7 fbk, device 1 fbk, device 2 [+] feedback
cy23s08 document #: 38-07265 rev. *h page 7 of 10 test circuits figure 7. test circuit 1 figure 8. test circuit 2 0.1 f v dd 0.1 f v dd clk out c load outputs gnd gnd test circuit for all parameters except t 8 v dd 0.1 f v dd clk out 10 pf outputs gnd gnd 1 k 1 k 0.1 f test circuit for t 8 , output slew rate on ?1h device test circuit # 2 [+] feedback
cy23s08 document #: 38-07265 rev. *h page 8 of 10 ordering information ordering code package type operating range status cy23s08sc?1 16-pin 150-mil soic commercial obsolete cy23s08sc?1t 16-pin 150-mil soic?tape and reel commercial obsolete cy23s08si?1 16-pin 150-mil soic industrial obsolete cy23s08si?1t 16-pin 150-mil soic?tape and reel industrial obsolete cy23s08sc?1h 16-pin 150-mil soic commercial obsolete cy23s08sc?1ht 16-pin 150-mil soic?tape and reel commercial obsolete cy23s08si?1h 16-pin 150-mil soic industrial not for new design cy23s08si?1ht 16-pin 150-mil soic?tape and reel industrial not for new design cy23s08zc?1h 16-pin 150-mil tssop commercial not for new design cy23s08zc?1ht 16-pin 150-mil tssop?tape and reel commercial obsolete cy23s08sc?2 16-pin 150-mil soic commercial not for new design cy23s08sc?2t 16-pin 150-mil soic?tape and reel commercial not for new design cy23s08si?2 16-pin 150-mil soic industrial not for new design cy23s08si?2t 16-pin 150-mil soic?tape and reel industrial not for new design cy23s08sc?2h 16-pin 150-mil soic commercial obsolete cy23s08sc?2ht 16-pin 150-mil soic?tape and reel commercial active cy23s08sc?3 16-pin 150-mil soic commercial obsolete cy23s08sc?3t 16-pin 150-mil soic?tape and reel commercial obsolete cy23s08sc?4 16-pin 150-mil soic commercial obsolete cy23s08sc?4t 16-pin 150-mil soic?tape and reel commercial obsolete cy23s08si?4 16-pin 150-mil soic industrial obsolete cy23s08si?4t 16-pin 150-mil soic?tape and reel industrial obsolete pb-free cy23s08sxc?1 16-pin 150-mil soic commercial active cy23s08sxc?1t 16-pin 150-mil soic?tape and reel commercial active cy23s08sxi?1h 16-pin 150-mil soic industrial active cy23s08sxi?1ht 16-pin 150-mil soic?tape and reel industrial active cy23s08zxc-1h 16-pin 150-mil tssop commercial active cy23s08sxc?2 16-pin 150-mil soic commercial active cy23s08sxc?2t 16-pin 150-mil soic?tape and reel commercial active cy23s08sxc?2h 16-pin 150-mil soic commercial active cy23s08sxc?2ht 16-pin 150-mil soic?tape and reel commercial active cy23s08sxi?2 16-pin 150-mil soic industrial active cy23s08sxi?2t 16-pin 150-mil soic?tape and reel industrial active cy23s08sxc-4 16-pin 150-mil soic commercial active cy23s08sxc-4t 16-pin 150-mil soic?tape and reel commercial active cy23s08sxi-4 16-pin 150-mil soic industrial active cy23s08sxi-4t 16-pin 150-mil soic?tape and reel industrial active [+] feedback
cy23s08 document #: 38-07265 rev. *h page 9 of 10 package drawings and dimensions figure 9. 16-pin (150-mil) soic s16 figure 10. 16-pin thin shrunk sm all outline package (4.40 mm body) z16 pin 1 id 0~8 1 8 916 seating plane 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.386[9.804] 0.393[9.982] 0.050[1.270] bsc 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] dimensions in inches[mm] min. max. 0.016[0.406] 0.010[0.254] x 45 0.004[0.102] reference jedec ms-012 part # s16.15 standard pkg. sz16.15 lead free pkg. package weight 0.15gms 51-85068-*b 4.90[0.193] 1.10[0.043] max. 0.65[0.025] 0.20[0.008] 0.05[0.002] 16 pin 1 id 6.50[0.256] seating plane 1 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] bsc. 5.10[0.200] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] bsc 0.25[0.010] 0-8 0.70[0.027] 0.50[0.020] 0.95[0.037] 0.85[0.033] plane gauge 51-85091-*a [+] feedback
document #: 38-07265 rev. *h revised november 3, 2008 page 10 of 10 all products and company names mentioned in this document may be the trademarks of their respective holders. cy23s08 ? cypress semiconductor corporation, 2001-2008. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products psoc psoc.cypress.com clocks & buffers clocks.cypress.com wireless wireless.cypress.com memories memory.cypress.com image sensors image.cypress.com psoc solutions general psoc.cypress.com/solutions low power/low voltage psoc.cypress.com/low-power precision analog psoc.cypress.com/precision-analog lcd drive psoc.cypress.com/lcd-drive can 2.0b psoc.cypress.com/can usb psoc.cypress.com/usb document title: cy23s08 3.3v zero delay buffer document number: 38-07265 rev. ecn no. orig. of change submission date description of change ** 110530 szv 12/02/01 change from spec number: 38-01107 to 38-07265 *a 122863 rbi 12/20/02 added power up requirements to operating conditions information. *b 130951 rgl 11/26/03 corrected the switching characteristics parameters to reflect the w152 device and new characterization. *c 204201 rgl see ecn corrected the block diagram *d 231100 rgl see ecn fixed typo in table 2. *e 378878 rgl see ecn added industrial temp and pb free devices added typical char data removed ?preliminary? *f 391564 rgl see ecn changed output-to-output skew typical value from 90ps to 45ps added cycle-to-cycle jitter (-2) typical value of 85ps *g 1442823 wwz/aesa see ecn updated ordering info with status update. added new pb-free part numbers. *h 2600345 wwz/pyrs 11/03/08 updated max frequency numb er from 133 mhz to 140 mhz on page 1 and page 4 load capacitance description [+] feedback
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